data/HTML/freemaster___m_p_c56xx_8h_source.html

00001 /******************************************************************************
00002 *
00003 * Freescale Semiconductor Inc.
00004 * (c) Copyright 2004-2011 Freescale Semiconductor
00005 * ALL RIGHTS RESERVED.
00006 *
00007 ****************************************************************************/
00019 #ifndef __FREEMASTER_MPC56xx_H
00020 #define __FREEMASTER_MPC56xx_H
00021
00022 /******************************************************************************
00023 * platform-specific default configuration
00024 ******************************************************************************/
00025
00026 /* compiler inline statement */
00027 #define FMSTR_INLINE static
00028
00029 /* use 32-bit (EX) commands by default */
00030 #ifndef FMSTR_USE_EX_CMDS
00031 #define FMSTR_USE_EX_CMDS 1
00032 #endif
00033
00034 /* do not use 16-bit (no-EX) commands by default */
00035 #ifndef FMSTR_USE_NOEX_CMDS
00036 #define FMSTR_USE_NOEX_CMDS 0
00037 #endif
00038
00039 /* at least one of EX or no-EX command handling must be enabled */
00040 #if !FMSTR_USE_EX_CMDS && !FMSTR_USE_NOEX_CMDS
00041     #error At least one of EX or no-EX command handling must be enabled (please set FMSTR_USE_EX_CMDS)
00042     #undef  FMSTR_USE_EX_CMDS
00043     #define FMSTR_USE_EX_CMDS 1
00044 #endif
00045
00046 /*****************************************************************************
00047 * Board configuration information
00048 ******************************************************************************/
00049
00050 #define FMSTR_PROT_VER           3      /* protocol version 3 */
00051 #define FMSTR_CFG_FLAGS  FMSTR_CFGFLAG_BIGENDIAN /* board info flags */
00052 #define FMSTR_CFG_BUS_WIDTH      1      /* data bus width */
00053 #define FMSTR_GLOB_VERSION_MAJOR 2      /* driver version */
00054 #define FMSTR_GLOB_VERSION_MINOR 0
00055 #define FMSTR_IDT_STRING "MPC56xx FreeMASTER Drv."
00056 #define FMSTR_TSA_FLAGS          0
00057
00058 /******************************************************************************
00059 * platform-specific types
00060 ******************************************************************************/
00061
00062 typedef unsigned char  FMSTR_U8;       /* smallest memory entity */
00063 typedef unsigned short FMSTR_U16;      /* 16bit value */
00064 typedef unsigned long  FMSTR_U32;      /* 32bit value */
00065
00066 typedef signed char    FMSTR_S8;       /* signed 8bit value */
00067 typedef signed short   FMSTR_S16;      /* signed 16bit value */
00068 typedef signed long    FMSTR_S32;      /* signed 32bit value */
00069
00070 #if FMSTR_REC_FLOAT_TRIG
00071 typedef float          FMSTR_FLOAT;      /* float value */
00072 #endif
00073
00074 typedef unsigned char  FMSTR_FLAGS;    /* type to be union-ed with flags (at least 8 bits) */
00075 typedef unsigned char  FMSTR_SIZE8;    /* one-byte size value */
00076 typedef signed short   FMSTR_INDEX;    /* general for-loop index (must be signed) */
00077
00078 typedef unsigned char  FMSTR_BCHR;     /* type of a single character in comm.buffer */
00079 typedef unsigned char* FMSTR_BPTR;     /* pointer within a communication buffer */
00080
00081 typedef unsigned long  FMSTR_SCISR;    /* data type to store SCI status register */
00082
00083 /******************************************************************************
00084 * communication buffer access functions
00085 ******************************************************************************/
00086
00087 void FMSTR_CopyMemory(FMSTR_ADDR nDestAddr, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize);
00088 FMSTR_BPTR FMSTR_CopyToBuffer(FMSTR_BPTR pDestBuff, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize);
00089 FMSTR_BPTR FMSTR_CopyFromBuffer(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize);
00090 void FMSTR_CopyFromBufferWithMask(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize);
00091
00092 /* mixed EX and non-EX commands may occur */
00093 #if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
00094 void FMSTR_SetExAddr(FMSTR_BOOL bNextAddrIsEx);
00095 #else
00096 /* otherwise, we always know what addresses are used, (ignore FMSTR_SetExAddr) */
00097 #define FMSTR_SetExAddr(bNextAddrIsEx)
00098 #endif
00099
00100 /*********************************************************************************
00101 * communication buffer access functions. Most of them are trivial simple on MPC56xx
00102 *********************************************************************************/
00103
00104 #define FMSTR_ValueFromBuffer8(pDest, pSrc) \
00105     ( (*((FMSTR_U8*)(pDest)) = *(FMSTR_U8*)(pSrc)), (((FMSTR_BPTR)(pSrc))+1) )
00106
00107 #define FMSTR_ValueFromBuffer16(pDest, pSrc) \
00108     ( (*((FMSTR_U16*)(pDest)) = *(FMSTR_U16*)(pSrc)), (((FMSTR_BPTR)(pSrc))+2) )
00109
00110 #define FMSTR_ValueFromBuffer32(pDest, pSrc) \
00111     ( (*((FMSTR_U32*)(pDest)) = *(FMSTR_U32*)(pSrc)), (((FMSTR_BPTR)(pSrc))+4) )
00112
00113
00114 #define FMSTR_ValueToBuffer8(pDest, src) \
00115     ( (*((FMSTR_U8*)(pDest)) = (FMSTR_U8)(src)), (((FMSTR_BPTR)(pDest))+1) )
00116
00117 #define FMSTR_ValueToBuffer16(pDest, src) \
00118     ( (*((FMSTR_U16*)(pDest)) = (FMSTR_U16)(src)), (((FMSTR_BPTR)(pDest))+2) )
00119
00120 #define FMSTR_ValueToBuffer32(pDest, src) \
00121     ( (*((FMSTR_U32*)(pDest)) = (FMSTR_U32)(src)), (((FMSTR_BPTR)(pDest))+4) )
00122
00123
00124 #define FMSTR_SkipInBuffer(pDest, nSize) \
00125     ( ((FMSTR_BPTR)(pDest)) + (nSize) )
00126
00127
00128 #define FMSTR_ConstToBuffer8  FMSTR_ValueToBuffer8
00129 #define FMSTR_ConstToBuffer16 FMSTR_ValueToBuffer16
00130
00131 /* EX address used only: fetching 32bit word */
00132 #if FMSTR_USE_EX_CMDS && !FMSTR_USE_NOEX_CMDS
00133     #define FMSTR_AddressFromBuffer(pDest, pSrc) \
00134         FMSTR_ValueFromBuffer32(pDest, pSrc)
00135     #define FMSTR_AddressToBuffer(pDest, nAddr) \
00136         FMSTR_ValueToBuffer32(pDest, nAddr)
00137
00138 /* no-EX address used only: fetching 16bit word  */
00139 #elif !FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
00140     #define FMSTR_AddressFromBuffer(pDest, pSrc) \
00141         FMSTR_ValueFromBuffer16(pDest, pSrc)
00142     #define FMSTR_AddressToBuffer(pDest, nAddr) \
00143         FMSTR_ValueToBuffer16(pDest, nAddr)
00144
00145 /* mixed addresses used, need to process it programatically */
00146 #else
00147     FMSTR_BPTR FMSTR_AddressFromBuffer(FMSTR_ADDR* pAddr, FMSTR_BPTR pSrc);
00148     FMSTR_BPTR FMSTR_AddressToBuffer(FMSTR_BPTR pDest, FMSTR_ADDR nAddr);
00149 #endif
00150
00151 #define FMSTR_GetS8(addr)  ( *(FMSTR_S8*)(addr) )
00152 #define FMSTR_GetU8(addr)  ( *(FMSTR_U8*)(addr) )
00153 #define FMSTR_GetS16(addr) ( *(FMSTR_S16*)(addr) )
00154 #define FMSTR_GetU16(addr) ( *(FMSTR_U16*)(addr) )
00155 #define FMSTR_GetS32(addr) ( *(FMSTR_S32*)(addr) )
00156 #define FMSTR_GetU32(addr) ( *(FMSTR_U32*)(addr) )
00157
00158 #if FMSTR_REC_FLOAT_TRIG
00159 #define FMSTR_GetFloat(addr) ( *(FMSTR_FLOAT*)(addr) )
00160 #endif
00161
00162 /****************************************************************************************
00163 * Other helper macros
00164 *****************************************************************************************/
00165
00166 /* This macro assigns C pointer to FMSTR_ADDR-typed variable */
00167 #define FMSTR_PTR2ADDR(tmpAddr,ptr) ( tmpAddr = (FMSTR_ADDR) (FMSTR_U8*) ptr )
00168 #define FMSTR_ARR2ADDR FMSTR_PTR2ADDR
00169
00170 /****************************************************************************************
00171 * Platform-specific configuration check
00172 *****************************************************************************************/
00173
00174 /* FlexCAN functionality tested on MCF52xx */
00175 #define FMSTR_CANHW_FLEXCAN 1
00176
00177 /****************************************************************************************
00178 * General peripheral space access macros
00179 *****************************************************************************************/
00180
00181 #define FMSTR_SETBIT32(base, offset, bit)     ((*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset))) |= bit)
00182 #define FMSTR_CLRBIT32(base, offset, bit)     ((*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset))) &= ~(bit))
00183 #define FMSTR_SETREG32(base, offset, value)   ((*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset))) = value)
00184 #define FMSTR_GETREG32(base, offset)          (*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset)))
00185 #define FMSTR_TSTBIT32(base, offset, bit)     (*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset)) & (bit))
00186
00187 #define FMSTR_SETBIT16(base, offset, bit)     ((*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset))) |= bit)
00188 #define FMSTR_CLRBIT16(base, offset, bit)     ((*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset))) &= ~(bit))
00189
00190 #define FMSTR_SETREG16(base, offset, value)   ((*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset))) = value)
00191 #define FMSTR_GETREG16(base, offset)          (*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset)))
00192
00193 #define FMSTR_SETREG8(base, offset, value)   ((*(volatile FMSTR_U8*)(((FMSTR_U32)(base))+(offset))) = value)
00194 #define FMSTR_GETREG8(base, offset)          (*(volatile FMSTR_U8*)(((FMSTR_U32)(base))+(offset)))
00195 /****************************************************************************************
00196 * SCI module constants
00197 *****************************************************************************************/
00198
00199 /* (UART)SCI module registers */
00200 #define FMSTR_UARTCR_OFFSET 0x12  /* 16bit register */
00201 #define FMSTR_LINIER_OFFSET 0x6   /* 16bit register */
00202 #define FMSTR_LINCR1_OFFSET 0x2   /* 16bit register */
00203 #define FMSTR_UARTSR_OFFSET 0x16  /* 16bit register */
00204 #define FMSTR_BDRL_DATA0_OFFSET   0x3B  /* 32bit register output*/
00205 #define FMSTR_BDRM_DATA4_OFFSET   0x3F  /* 32bit register input*/
00206
00207 /* UARTCR Control Register 1 bits */
00208 #define FMSTR_UARTCR_TXEN        0x0010
00209 #define FMSTR_UARTCR_RXEN        0x0020
00210
00211 /* LINIER Control Register 1 bits */
00212 #define FMSTR_LINIER_DRIE       0x0004
00213 #define FMSTR_LINIER_DTIE       0x0002
00214
00215
00216 /* UART(SCI) Status registers bits */
00217
00218 #define FMSTR_SCISR_RDRF       0x0004   //DRF
00219 #define FMSTR_SCISR_TDRE       0x0002   //DTF
00220
00221
00222 /*******************************************************************************************
00223 * SCI access macros
00224 *****************************************************************************************/
00225
00226 /* transmitter enable/disable */
00227 #define FMSTR_SCI_TE() FMSTR_SETBIT16(FMSTR_SCI_BASE, FMSTR_UARTCR_OFFSET, FMSTR_UARTCR_TXEN)
00228 #define FMSTR_SCI_TD() FMSTR_CLRBIT16(FMSTR_SCI_BASE, FMSTR_UARTCR_OFFSET, FMSTR_UARTCR_TXEN)
00229
00230 /* receiver enable/disable */
00231 #define FMSTR_SCI_RE() FMSTR_SETBIT16(FMSTR_SCI_BASE, FMSTR_UARTCR_OFFSET, FMSTR_UARTCR_RXEN)
00232 #define FMSTR_SCI_RD() FMSTR_CLRBIT16(FMSTR_SCI_BASE, FMSTR_UARTCR_OFFSET, FMSTR_UARTCR_RXEN)
00233
00234 #define FMSTR_SCI_TE_RE() FMSTR_SETBIT16(FMSTR_SCI_BASE, FMSTR_UARTCR_OFFSET, FMSTR_UARTCR_RXEN | FMSTR_UARTCR_TXEN)
00235
00236 /* Transmitter-empty interrupt enable/disable */
00237 #define FMSTR_SCI_ETXI() FMSTR_SETBIT16(FMSTR_SCI_BASE, FMSTR_LINIER_OFFSET, FMSTR_LINIER_DTIE)
00238 #define FMSTR_SCI_DTXI() FMSTR_CLRBIT16(FMSTR_SCI_BASE, FMSTR_LINIER_OFFSET, FMSTR_LINIER_DTIE)
00239
00240 /* Receiver-full interrupt enable/disable */
00241 #define FMSTR_SCI_ERXI() FMSTR_SETBIT16(FMSTR_SCI_BASE, FMSTR_LINIER_OFFSET, FMSTR_LINIER_DRIE)
00242 #define FMSTR_SCI_DRXI() FMSTR_CLRBIT16(FMSTR_SCI_BASE, FMSTR_LINIER_OFFSET, FMSTR_LINIER_DRIE)
00243
00244 /* Tranmsit character */
00245 #define FMSTR_SCI_PUTCHAR(ch) FMSTR_SETREG8(FMSTR_SCI_BASE, FMSTR_BDRL_DATA0_OFFSET, (ch))
00246
00247 /* Get received character */
00248 #define FMSTR_SCI_GETCHAR() ((FMSTR_U8) FMSTR_GETREG8(FMSTR_SCI_BASE, FMSTR_BDRM_DATA4_OFFSET))
00249
00250 /* read status register */
00251 #define FMSTR_SCI_GETSR()   FMSTR_GETREG16(FMSTR_SCI_BASE, FMSTR_UARTSR_OFFSET)
00252
00253 /* read & clear status register  */
00254 FMSTR_INLINE FMSTR_SCISR FMSTR_SCI_RDCLRSR(void)
00255 {
00256     FMSTR_SCISR sr = FMSTR_GETREG16(FMSTR_SCI_BASE, FMSTR_UARTSR_OFFSET);
00257     FMSTR_SETREG16(FMSTR_SCI_BASE, FMSTR_UARTSR_OFFSET, (FMSTR_U16) (sr & (FMSTR_SCISR_RDRF|FMSTR_SCISR_TDRE)));
00258     return sr;
00259 }
00260
00261 /****************************************************************************************
00262 * FCAN module constants
00263 *****************************************************************************************/
00264
00265 /* FCAN module MB CODEs */
00266 #define FMSTR_FCANMB_CODE_MASK      0x0F   /* defines mask of codes */
00267
00268 #define FMSTR_FCANMB_CRXVOID        0x00   /* buffer void after received data read-out */
00269 #define FMSTR_FCANMB_CRXEMPTY       0x04   /* active and empty */
00270
00271 #define FMSTR_FCANMB_CTXTRANS_ONCE  0x0C   /* Initialize transmiting data from buffer */
00272 #define FMSTR_FCANMB_CTXREADY       0x08   /* Message buffer not ready for transmit */
00273
00274 /* FCAN module registers offsets */
00275 #define FMSTR_FCANTMR_OFFSET   0x08
00276 #define FMSTR_FCANIER2_OFFSET  0x24
00277 #define FMSTR_FCANIER1_OFFSET  0x28
00278 #define FMSTR_FCANIFR2_OFFSET  0x2C
00279 #define FMSTR_FCANIFR1_OFFSET  0x30
00280 #define FMSTR_FCANRXFG_OFFSET  (0x80 + ((FMSTR_FLEXCAN_RXMB) * 0x10))
00281 #define FMSTR_FCANTXFG_OFFSET  (0x80 + ((FMSTR_FLEXCAN_TXMB) * 0x10))
00282
00283 /* FCAN MB registers offsets (must also add FCANxxFG_OFFSET) */
00284 #define FMSTR_FCMBCSR   0x00
00285 #define FMSTR_FCMBIDR0  0x04
00286 #define FMSTR_FCMBIDR1  0x05
00287 #define FMSTR_FCMBIDR2  0x06
00288 #define FMSTR_FCMBIDR3  0x07
00289 #define FMSTR_FCMBDSR0  0x08
00290 #define FMSTR_FCMBDSR1  0x09
00291 #define FMSTR_FCMBDSR2  0x0A
00292 #define FMSTR_FCMBDSR3  0x0B
00293 #define FMSTR_FCMBDSR4  0x0C
00294 #define FMSTR_FCMBDSR5  0x0D
00295 #define FMSTR_FCMBDSR6  0x0E
00296 #define FMSTR_FCMBDSR7  0x0F
00297
00298 /* FCAN CANMSCSR */
00299 #define FMSTR_FCANCTRL_IDE     0x20
00300 #define FMSTR_FCANCTRL_STD_RTR 0x10
00301 #define FMSTR_FCANCTRL_EXT_RTR 0x10
00302 #define FMSTR_FCANCTRL_EXT_SRR 0x40
00303
00304 /* FCAN ID flags */
00305 #define FMSTR_FCANID0_EXT_FLG  0x80
00306
00307 /* FCAN: enable/disable CAN RX/TX interrupts */
00308 #define FMSTR_FCAN_ETXI() ( ((FMSTR_FLEXCAN_TXMB)&0x20) ? \
00309                             FMSTR_SETBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER2_OFFSET, (1<<((FMSTR_FLEXCAN_TXMB)-32))):\
00310                             FMSTR_SETBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER1_OFFSET, (1<<(FMSTR_FLEXCAN_TXMB))) )
00311 #define FMSTR_FCAN_DTXI() ( ((FMSTR_FLEXCAN_TXMB)&0x20) ? \
00312                             FMSTR_CLRBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER2_OFFSET, (1<<((FMSTR_FLEXCAN_TXMB)-32))):\
00313                             FMSTR_CLRBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER1_OFFSET, (1<<(FMSTR_FLEXCAN_TXMB))) )
00314
00315 #define FMSTR_FCAN_ERXI() ( ((FMSTR_FLEXCAN_RXMB)&0x20) ? \
00316                             FMSTR_SETBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER2_OFFSET, (1<<((FMSTR_FLEXCAN_RXMB)-32))):\
00317                             FMSTR_SETBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER1_OFFSET, (1<<(FMSTR_FLEXCAN_RXMB))) )
00318 #define FMSTR_FCAN_DRXI() ( ((FMSTR_FLEXCAN_RXMB)&0x20) ? \
00319                             FMSTR_CLRBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER2_OFFSET, (1<<((FMSTR_FLEXCAN_RXMB)-32))):\
00320                             FMSTR_CLRBIT32(FMSTR_CAN_BASE, FMSTR_FCANIER1_OFFSET, (1<<(FMSTR_FLEXCAN_RXMB))) )
00321
00322 /* FCAN: read RX status register */
00323 #define FMSTR_FCAN_TEST_RXFLG() ( ((FMSTR_FLEXCAN_RXMB)&0x20) ? \
00324                             FMSTR_TSTBIT32(FMSTR_CAN_BASE, FMSTR_FCANIFR2_OFFSET, (1<<((FMSTR_FLEXCAN_RXMB)-32))):\
00325                             FMSTR_TSTBIT32(FMSTR_CAN_BASE, FMSTR_FCANIFR1_OFFSET, (1<<(FMSTR_FLEXCAN_RXMB))) )
00326
00327 #define FMSTR_FCAN_CLEAR_RXFLG() ( ((FMSTR_FLEXCAN_RXMB)&0x20) ? \
00328                             FMSTR_SETREG32(FMSTR_CAN_BASE, FMSTR_FCANIFR2_OFFSET, (1<<((FMSTR_FLEXCAN_RXMB)-32))):\
00329                             FMSTR_SETREG32(FMSTR_CAN_BASE, FMSTR_FCANIFR1_OFFSET, (1<<(FMSTR_FLEXCAN_RXMB))) )
00330
00331 /* FCAN: read TX status register */
00332 #define FMSTR_FCAN_TEST_TXFLG() ( ((FMSTR_FLEXCAN_TXMB)&0x20) ? \
00333                             FMSTR_TSTBIT32(FMSTR_CAN_BASE, FMSTR_FCANIFR2_OFFSET, (1<<((FMSTR_FLEXCAN_TXMB)-32))):\
00334                             FMSTR_TSTBIT32(FMSTR_CAN_BASE, FMSTR_FCANIFR1_OFFSET, (1<<(FMSTR_FLEXCAN_TXMB))) )
00335
00336 //#define FMSTR_FCAN_TEST_TXFLG()   FMSTR_TSTBIT32(FMSTR_CAN_BASE, FMSTR_FCANIFR_OFFSET, (1<<(FMSTR_FLEXCAN_TXMB)))
00337
00338 /* FCAN: read TX MB status register */
00339 #define FMSTR_FCAN_GET_MBSTATUS() (FMSTR_GETREG8(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET+FMSTR_FCMBCSR)&FMSTR_FCANMB_CODE_MASK)
00340
00341 /* FCAN: id to idr translation */
00342 #define FMSTR_FCAN_MAKEIDR0(id) ((FMSTR_U8)( ((id)&FMSTR_CAN_EXTID) ? ((((id)>>24)&0x1f) | FMSTR_FCANID0_EXT_FLG) : (((id)>>6)&0x1f) ))
00343 #define FMSTR_FCAN_MAKEIDR1(id) ((FMSTR_U8)( ((id)&FMSTR_CAN_EXTID) ? ((id)>>16) : ((id)<<2) ))
00344 #define FMSTR_FCAN_MAKEIDR2(id) ((FMSTR_U8)( ((id)&FMSTR_CAN_EXTID) ? ((id)>>8) : 0 ))
00345 #define FMSTR_FCAN_MAKEIDR3(id) ((FMSTR_U8)( ((id)&FMSTR_CAN_EXTID) ? (id) : 0 ))
00346
00347 /* FCAN reception, configuring the buffer, just once at the initialization phase */
00348 #define FMSTR_FCAN_RINIT(idr0, idr1, idr2, idr3) \
00349     FMSTR_MACROCODE_BEGIN() \
00350         (((idr0)&FMSTR_FCANID0_EXT_FLG) ? \
00351         (FMSTR_SETREG16(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET + FMSTR_FCMBCSR, (FMSTR_FCANMB_CRXVOID<<8 | FMSTR_FCANCTRL_IDE | FMSTR_FCANCTRL_EXT_SRR))) : \
00352         (FMSTR_SETREG16(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET + FMSTR_FCMBCSR, (FMSTR_FCANMB_CRXVOID<<8 |  FMSTR_FCANCTRL_EXT_SRR))));\
00353         FMSTR_SETREG32(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET + FMSTR_FCMBIDR0, ((idr0)<<24) | ((idr1)<<16) | ((idr2)<<8) | (idr3) );\
00354     FMSTR_MACROCODE_END()
00355
00356 /* FCAN transmission, configuring the buffer, just once at the initialization phase */
00357 #define FMSTR_FCAN_TINIT(idr0, idr1, idr2, idr3) \
00358     FMSTR_MACROCODE_BEGIN() \
00359       (((idr0)&FMSTR_FCANID0_EXT_FLG) ? \
00360       (FMSTR_SETREG16(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET + FMSTR_FCMBCSR, (FMSTR_FCANMB_CTXREADY<<8 | FMSTR_FCANCTRL_IDE))) : \
00361       (FMSTR_SETREG16(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET + FMSTR_FCMBCSR, (FMSTR_FCANMB_CTXREADY<<8 ))));\
00362     FMSTR_MACROCODE_END()
00363
00364 /* FCAN reception, configuring the buffer for receiving (each time receiver is re-enabled) */
00365 #define FMSTR_FCAN_RCFG() \
00366     FMSTR_SETREG8(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET + FMSTR_FCMBCSR, FMSTR_FCANMB_CRXEMPTY)
00367
00368 /* FCAN: CAN transmission */
00369 typedef struct
00370 {
00371     FMSTR_U8 nDataIx;
00372 } FMSTR_FCAN_TCTX;
00373
00374 /* FCAN transmission, put one data byte into buffer */
00375 #define FMSTR_FCAN_TLEN(pctx, len) \
00376     FMSTR_SETREG8(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET+FMSTR_FCMBCSR+1, (FMSTR_U8)((len & 0x0f) | \
00377         (FMSTR_GETREG8(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET+FMSTR_FCMBCSR+1)&(FMSTR_FCANCTRL_IDE | FMSTR_FCANCTRL_EXT_SRR | FMSTR_FCANCTRL_EXT_RTR))))
00378
00379 /* FCAN transmission, put one data byte into buffer */
00380 #define FMSTR_FCAN_PUTBYTE(pctx, dataByte) \
00381     FMSTR_MACROCODE_BEGIN() \
00382         FMSTR_SETREG8(FMSTR_CAN_BASE, (FMSTR_FCANTXFG_OFFSET + FMSTR_FCMBDSR0) + ((pctx)->nDataIx), (dataByte) ); \
00383         (pctx)->nDataIx++; \
00384     FMSTR_MACROCODE_END()
00385
00386 /* FCAN: CAN transmission, configuring the buffer before each transmission */
00387 #define FMSTR_FCAN_TCFG(pctx) \
00388     FMSTR_MACROCODE_BEGIN() \
00389         (pctx)->nDataIx = 0; \
00390     FMSTR_MACROCODE_END()
00391
00392 /* FCAN: CAN transmission, preparing the buffer before each transmission */
00393 #define FMSTR_FCAN_TID(pctx, idr0, idr1, idr2, idr3) \
00394     FMSTR_MACROCODE_BEGIN() \
00395         FMSTR_SETREG32(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET+FMSTR_FCMBIDR0, ((idr0)<<24) | ((idr1)<<16) | ((idr2)<<8) | (idr3) ); \
00396     FMSTR_MACROCODE_END()
00397
00398 /* FCAN transmission, set transmit priority */
00399 #define FMSTR_FCAN_TPRI(pctx, txPri) /* in FCAN module is not implemented */
00400
00401 /* FCAN transmission, final firing of the buffer */
00402 #define FMSTR_FCAN_TX(pctx) \
00403         FMSTR_SETREG8(FMSTR_CAN_BASE, FMSTR_FCANTXFG_OFFSET + FMSTR_FCMBCSR, (FMSTR_FCANMB_CTXTRANS_ONCE & 0x0f) )
00404
00405 /* FCAN reception */
00406 typedef struct
00407 {
00408     FMSTR_U8 nDataIx;
00409 } FMSTR_FCAN_RCTX;
00410
00411 /* FCAN reception, lock frame */
00412 #define FMSTR_FCAN_RX(pctx) \
00413     (pctx)->nDataIx = 0;
00414
00415 /* FCAN reception, test if received message ID matches the one given, TRUE if matching */
00416 #define FMSTR_FCAN_TEST_RIDR(pctx, idr0, idr1, idr2, idr3) \
00417     ( (idr0 & FMSTR_FCANID0_EXT_FLG) ? \
00418         /* ext id compare */ \
00419         ( ((((idr0)<<24) | ((idr1)<<16) | ((idr2)<<8) | (idr3))&0x1f000000)==((FMSTR_GETREG32(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET+FMSTR_FCMBIDR0))&0x1f000000) ) : \
00420         /* std id compare */ \
00421         ( (((idr0)<<8) | (idr1))==((FMSTR_GETREG16(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET+FMSTR_FCMBIDR0))&0x1ffc) ) )
00422
00423 /* FCAN reception, get receviced frame length */
00424 #define FMSTR_FCAN_RLEN(pctx) \
00425     (FMSTR_GETREG8(FMSTR_CAN_BASE, FMSTR_FCANRXFG_OFFSET+FMSTR_FCMBCSR+1) & 0x0f)
00426
00427 /* FCAN reception, get one received byte */
00428 #define FMSTR_FCAN_GETBYTE(pctx) \
00429         ((FMSTR_U8) (FMSTR_GETREG8(FMSTR_CAN_BASE, (FMSTR_FCANRXFG_OFFSET + FMSTR_FCMBDSR0) + ((pctx)->nDataIx) ))); \
00430         (pctx)->nDataIx++
00431
00432 /* FCAN reception, unlock the buffer */
00433 #define FMSTR_FCAN_RFINISH(pctx) \
00434     FMSTR_SETBIT16(FMSTR_CAN_BASE, FMSTR_FCANTMR_OFFSET, 0)
00435
00436 #endif /* __FREEMASTER_MPC56xx_H */